Purple background indicates Design Methods Sessions. Grey indicates Embedded Systems.

Ses#	Session 36	Session 37	Session 38	Session 39	Session 40
8:30 to 10:00	Advances in Timing and Simulation	PANEL: Formal Verification Methods: Getting Around the Brick Wall	Routing and Buffering	System on Chip Design	Timing Analysis and Memory Optimization for Embedded Systems
BREAK 10:00 - 10:30
Ses#	Session 41	Session 42	Session 43	Session 44	Session 45
10:30 to 12:00	Processors and Accelerators for Embedded Applications	PANEL: What is the Next EDA Driver?	Cross-Talk Noise Analysis and Management	Test Cost Reduction for SoCs	Scheduling Techniques for Embedded Systems
KEYNOTE - 1:00 - 1:45 - Room: Auditorium B Software and Silicon - Where's the Equilibrium? Jerry Fiddler - Chairman and Founder, Wind River
Ses#	Session 46	Session 47	Session 48	Session 49	Session 50
2:00 to 4:00	SPECIAL SESSION: Designing SoCs for Yield Improvement	Advances in SAT	Inductance and Substrate Analysis	Development of Processors and Communication Networks for Embedded Systems	Moving Towards More Effective Validation
BREAK 4:00 - 4:30
Ses#	Session 51	Session 52	Session 53	Session 54	Session 55
4:30 to 6:00	SPECIAL SESSION: Energy Efficient Mobile Computing	Floorplanning and Placement	Circuit Effects in Static Timing	Design Space Exploration for Embedded Systems	Behavioral Synthesis